The influence of Line Edge Roughness in scatterometry-based CD metrology

Semiconductor industry still follows the Moore's Law so that the Critical Dimension (CD) of integrated circuits is shrinking. Many problems have been overcome until now, with new issue entering the game - the Line Edge/Width Roughness (LER/LWR), defined as variations of a given edge's position or feature's width occurring quickly over their length. Reports state that LER/LWR is gaining in impact on the performance of lithography-fabricated circuits. This is the reason for the need to monitor the LER/LWR so that it never exceeds certain limits. International Technology Roadmap for Semiconductors (ITRS) states about monitoring the LER/LWR that "manufacturable solutions are NOT known". The motivation for our simulation work is to verify if scatterometry, which is already successfully used in semiconductor industry, can be used to "manufacturably" access the LER/LWR information. We show that one scatterometric measurement is not sufficient for this purpose, as the LER/LWR-affected structure is no different from LER/LWR-free structure of another CD. Only adding a second measurement with different polarization of light makes LER/LWR detectable by introducing an observable difference.