An Efficient FPGA Hardware Architecture for Plenoptic 3D Image Processing Algorithm

In recent years, 3D image processing algorithms are being extensively used in computer vision applications. Unlike stereo camera system, Plenoptic camera can be used in a monocular setup to estimate depth. It captures lightfield with the help of micro-lens array. The corresponding depth estimation algorithm consists of a substantial number of recurrent operations. General purpose processor system results in a large execution time due to its sequential architecture. Moreover, graphics processing unit is not an energy efficient solution and therefore it cannot be used in embedded applications with scarce power resources. To improve the performance of such algorithms, we propose an energy efficient FPGA hardware architecture that utilizes its highly concurrent structure. Moreover, a modified Plenoptic depth estimation algorithm is presented which works on a single frame. It is adapted with respect to the hardware that is achieved via several optimizations, including parallelization, pipelining and efficient memory access. This system is designed, realized and thereafter evaluated. The results show that FPGA hardware design reduces the execution time of the presented algorithm.